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| Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance PHB11N06LT, PHD11N06LT SYMBOL d QUICK REFERENCE DATA VDSS = 55 V ID = 11 A g s RDS(ON) 150 m (VGS = 5 V) RDS(ON) 130 m (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHB11N06LT is supplied in the SOT404 surface mounting package. The PHD11N06LT is supplied in the SOT428 surface mounting package. PINNING PIN 1 2 3 tab gate drain 1 source DESCRIPTION SOT428 tab SOT404 tab 2 2 3 drain 1 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 13 11 7.6 44 36 175 UNIT V V V A A A W C 1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package September 1998 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET ESD LIMITING VALUE SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS PHB11N06LT, PHD11N06LT MIN. - MAX. 2 UNIT kV Human body model (100 pF, 1.5 k) THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. SOT78 package, in free air SOT428 and SOT404 package, pcb mounted, minimum footprint 60 50 MAX. 4.17 UNIT K/W K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; IG = 1 mA; VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 5.5 A VGS = 5 V; ID = 5.5 A Tj = 175C Forward transconductance VDS = 25 V; ID = 5.5 A Gate source leakage current VGS = 5 V; VDS = 0 V Tj = 175C Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance VDS = 55 V; VGS = 0 V; Tj = 175C ID = 11 A; VDD = 44 V; VGS = 5 V Tj = -55C MIN. 55 50 10 1.0 0.5 4 TYP. MAX. UNIT 1.5 100 120 250 10 0.02 0.05 6.1 1.3 3.2 6 23 18 18 3.5 7.5 250 34 35 2.0 2.3 130 150 315 1 20 10 500 16 35 30 30 330 50 50 V V V V V V m m m S A A A A nC nC nC ns ns ns ns nH nH pF pF pF VDD = 30 V; ID = 5 A; VGS = 5 V; RG = 10 Resistive load Measured from tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz September 1998 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHB11N06LT, PHD11N06LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 11 A; VGS = 0 V IF = 11 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 0.95 34 57 11 44 1.2 A A V ns nC AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 10 UNIT mJ Drain-source non-repetitive ID 10 A; VDD 25 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 ; Tmb = 25 C energy September 1998 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHB11N06LT, PHD11N06LT 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Transient thermal impedance, Zth j-mb (K/W) 1 0.1 0.01 P D tp D= tp T t 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 1us T 10us 100us 1ms 10ms pulse width, tp (s) 0.1s 1s 10s PHB11N06LT Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating 10 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 120 110 100 90 80 70 60 50 40 30 20 10 0 ID, Drain current (Amps) 10 V 5V PHB11N06LT Tj = 25 C 3.6 V 3.4 V 3.2 V 8 6 4 3V 2.8 V VGS = 2.6 V 2 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 0 2 4 6 8 VDS, Drain-Source voltage (Volts) 10 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS RDS(on), Drain-Source on resistance (Ohms) 2.6V Tj = 25 C 2.8V 3V 3.2V 3.4V 3.6V 100 ID, Drain current (Amps) PHB11N06LT 0.5 10 RD S(O N) = S VD /ID tp = 0.4 10 us 0.3 100 us DC 1 10 ms 0.1 1 ms 0.2 VGS = 5 V 10 V 0.1 0 1 10 VDS, Drain-source voltage (Volts) 100 0 2 4 6 ID, Drain current (Amps) 8 10 PHB11N06LT Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS September 1998 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHB11N06LT, PHD11N06LT 10 Drain current, ID (A) VDS > ID x RDS(on) PHB11N06LT 2.5 VGS(TO) / V max. BUK959-60 8 2 typ. 6 1.5 min. 4 175 C Tj = 25 C 0 0 1 2 3 Gate-source voltage, VGS (V) 4 5 1 2 0.5 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction 8 7 6 5 4 3 2 1 0 Transconductance, gfs (S) VDS > ID x RDS(on) PHB11N06LT 1E-01 Tj = 25 C 1E-02 2% typ 98% Tj = 175 C 1E-03 1E-04 1E-05 0 2 4 6 Drain current, ID (A) 8 10 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V BUK959-60 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS 2.5 a Rds(on) normlised to 25degC 1000 Capacitances, Ciss, Coss, Crss (pF) PHB11N06LT 2 Ciss 1.5 100 Coss Crss 1 0.5 -100 -50 0 50 Tmb / degC 100 150 200 10 0.1 1 10 Drain-source voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 5.5 A; VGS = 5 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz September 1998 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHB11N06LT, PHD11N06LT 15 VGS, Gate-Source voltage (Volts) VDD = 44 V ID = 11 A Tj = 25 C PHB11N06LT 120 110 100 90 80 70 60 50 WDSS% 10 5 40 30 20 10 0 0 2 4 6 8 Qg, Gate charge (nC) 10 12 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb) 20 Source-drain diode current, IF (A) VGS = 0V PHB11N06LT + L VDS 175 C Tj = 25 C VDD 15 10 VGS 0 T.U.T. -ID/100 5 RGS 0 0 0.2 0.4 0.6 0.8 1 Source-drain voltage, VSDS (V) 1.2 1.4 R 01 shunt Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) September 1998 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g 10.3 max PHB11N06LT, PHD11N06LT 4.5 max 1.4 max 11 max 15.4 2.5 0.85 max (x2) 2.54 (x2) 0.5 Fig.17. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". September 1998 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET MECHANICAL DATA PHB11N06LT, PHD11N06LT Dimensions in mm : Net Mass: 1.4 g seating plane 6.73 max 1.1 2.38 max 0.93 max 5.4 tab 4 min 6.22 max 10.4 max 4.6 2 1 3 0.5 min 0.3 0.5 0.5 0.8 max (x2) 2.285 (x2) Fig.19. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 2.5 1.5 4.57 Fig.20. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". September 1998 8 Rev 1.000 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHB11N06LT, PHD11N06LT This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1998 9 Rev 1.000 |
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